Wafer-level Chip Scale package (WLCSP) techniques are often used for high density component packaging for portable computing devices, mobile handsets, image sensors, etc. WLCSP techniques can include packaging, testing, and performing burn-in operations prior to singulation of the wafer into individual IC chips. During singulation, a dicing machine saws the wafer along scribe lines to separate the individual IC chips. Once an IC chip has been singulated, the IC chip can be mounted on a printed circuit board (PCB).
A typical WLSCP IC chip uses metal (e.g., solder) rather than wires or pins for mounting onto a PCB. Typically, wire-bond pads are designed and fabricated along the edges on the top or circuit side of the IC chip. In most cases, the wire-bond pads are of small geometry and are also too close to each other for WLCSP-size solder ball formation. A redistribution layer (RDL) includes metal traces which make contact with the wire-bond pads and relocate the signals to desired locations within the IC chip where greater real estate provides space for forming larger attachment pads. The larger attachment pads can be used for placement of larger diameter solder balls. Solder balls can be deposited to at the new locations to facilitate assembly onto PCBs or other IC devices.
Since the solder balls are formed only on the top or circuit side of the wafer, the WLCSP cannot be used for device stacking applications due to the absence of connection pads on the bottom side of the wafer that are electrically connected to the top side. The presence of the I/O pads on the top or active circuit side can render WLCSP unfeasible for some sensor applications due to physical blocking of sensor elements by I/O features.
Currently, these problems are addressed by forming conductive “vias” through the core silicon or substrate to achieve top to bottom side electrical connections in the WLCSP. For example, an atmospheric downstream plasma (ADP) process can be used to etch cavities in the IC wafer's core silicon by using an aluminum mask. Dielectric material and metal conductors are deposited onto the “sidewall” of the cavities. The cavities are then filled with a polymer. The silicon wafer is “thinned” to expose the conductor metal on the other side of the wafer. In another example, a Through-Wafer-Interconnect (TWI) process forms vias through the silicon core material, insulates the sidewalls and then fills the vias with conductor to achieve electrical connectivity from one side of the IC wafer to the other side. Some package assembly contractors are also developing similar Through-Silicon-Via technologies to achieve “top-bottom” electrical connectivity.